1. Field of the Invention
The present invention relates to a multilevel non-volatile semiconductor memory for recording data of at least three levels to a memory cell and a method of writing the data.
2. Description of the Related Art
In non-volatile semiconductor memory apparatuses such as flash memories, a two-level memory cell structure is normally adopted, which records data having two values, "0" and "1", in one memory cell transistor.
Along with the recent demands for larger capacities of semiconductor memories, a so-called multilevel non-volatile semiconductor memory which records data of at least 3 levels in one memory cell has been proposed (for example, refer to "A Multi-Level 32 Mb Flash Memory" 1995 ISSCC, from p. 132).
FIG. 1 is a view of the relationship of a level of a threshold voltage Vth and data contents when recording data composed of 2 bits having four values in one transistor in a NAND flash memory.
In FIG. 1, the ordinate indicates the threshold voltage Vth and the abscissa indicates a distribution frequency of a memory transistor.
The two-bit data comprising the data to be recorded in one transistor is indicated by (IO.sub.n+1, IO.sub.n). There are four states (IO.sub.n+1, IO.sub.n)=(1, 1), (1, 0), (0, 1), and (0, 0). Namely, there are four states of the data "0", data "1", data "2", and data "3".
Also, a NAND flash memory has been proposed which performs a write operation of multi-level data in page units (word line units) (for example, refer to 1996 IEEE International Solid-State Circuits Conference, ISSCC96/SESSION 2/FLASH MEMORY/PAPER TP 2.1:A 3.3V 128 Mb Multi-Level NAND Flash Memory For Mass Storage Application, pp. 32 to 33).
FIG. 2 is a circuit diagram of the configuration of the core part of a NAND flash memory for performing a write operation in page units disclosed in the above reference.
In FIG. 2, reference number 1 indicates a memory cell array, 2 a write/read control circuit, and BL1 and BL2 bit lines.
The memory cell array 1 comprises memory strings A0 and A1 comprising memory cells respectively connected to common word lines WL0 to WL15. The memory string A0 is connected to the bit line BL1 and the memory string A1 is connected to the bit line BL2.
The memory string A0 has a NAND string comprised of serially connected memory cell transistors MT0A to MT15A comprising non-volatile semiconductor memories having floating gates. A drain of the memory cell transistor MT0A of the NAND string is connected to the bit line BL1 via a select gate SG1A, while a source of the memory transistor MT15A is connected to the reference potential line VGL via a select gate SG2A.
The memory string A1 has a NAND string comprised of serially connected memory cell transistors MT0B to MT15B comprising non-volatile semiconductor memories having floating gates. A drain of the memory cell transistor MT0B of the NAND string is connected to the bit line BL2 via a select gate SG1B, while a source of the memory transistor MT15B is connected to the reference potential line VGL via a select gate SG2B.
Gates of the select gates SG1A and SG1B are commonly connected to a select signal supply line SSL, while gates of the select gates SG2A and SG2B are commonly connected to a select signal supply line GSL.
The write/read control circuit 2 comprises n-channel MOS (NMOS) transistors NT1 to NT17, a p-channel MOS (PMOS) transistor PT1, and latch circuits Q1 and Q2 combining inputs and outputs of an inverter.
The NMOS transistor NT1 is connected between a supply line of a power source voltage Vcc and the bit line BL1 and the gate is connected to a supply line of an inhibit signal IHB1. The NMOS transistor NT2 is connected between the supply line of the power source voltage Vcc and the bit line BL2 and the gate is connected to a supply line of an inhibit signal IHB2.
A depletion NMOS transistor NT18 is connected between a connecting point of an NMOS transistor NT3 and an NMOS transistor NT1 and a connecting point of the memory string A0 and the bit line BL1. A depletion NMOS transistor NT19 is connected between a connecting point of an NMOS transistor NT4 and an NMOS transistor NT2 and a connecting point of the memory string A1 and the bit line BL2. Gates of the NMOS transistors NT18 and NTl9 are connected to a decouple signal supply line DCPL.
NMOS transistors NT3, NT5, and NT16 are connected in series between a connecting point of the depletion NMOS transistor NT18 and the NMOS transistor NT1 and a bus line IOi, while NMOS transistors NT4, NT7, and NT17 are connected in series between a connecting point of the depletion NMOS transistor NT19 and the NMOS transistor NT2 and a bus line IO.sub.i+1.
Also, a connecting point of the NMOS transistors NT3 and NT5 and a connecting point of the NMOS transistors NT4 and NT7 are grounded via an NMOS transistor NT6 and connected to a drain of the PMOS transistor PT1 and gates of NMOS transistors NT8 and NT13. A gate of the NMOS transistor NT6 is connected to a supply line of a reset signal RST, a source of the PMOS transistor PT1 is connected to a supply line of the power source voltage Vcc, and a gate of the PMOS transistor PT1 is connected to a supply line of a signal Vref.
A first memory node N1a of the latch circuit Q1 is connected to a connecting point of NMOS transistors NT5 and NT16, while a second memory node N1b is grounded via NMOS transistors NT8 to NT10 connected in series.
A first memory node N2a of the latch circuit Q2 is connected to a connecting point of the NMOS transistors NT7 and NT17, while a second memory node N2b is grounded via NMOS transistors NT13 to NT15.
A connecting point of the NMOS transistors NT8 and NT9 is grounded via the NMOS transistors NT11 and NT12 connected in series.
A gate of the NMOS transistor NT9 is connected to a first memory node N2a of the latch circuit Q2, a gate of the NMOS transistor NT10 is connected to a supply line of a control signal (.phi.LAT2, a gate of the NMOS transistor NT11 is connected to a second memory node N2b, a gate of the NMOS transistor NT12 is connected to a supply line of a control signal .phi.LAT1, and gates of the NMOS transistors NT14 and NT15 are connected to a supply line of a latch control .phi.LAT3.
A gate of the NMOS transistor NT16 serving as a column gate is connected to a supply line of a signal Yi and a gate of the NMOS transistor NT17 is connected to a supply line of a signal Yi+1.
FIG. 3A is a timing chart at the time of reading and FIG. 3B is a timing chart at the time of writing (programming).
As will be understood from FIG. 3B, writing of four values is carried out in three steps. The procedure moves on to the next step at the stage when it is judged that all cells to which the write operation was originally to be performed in page units in each of the steps are sufficiently written in.
A read operation will be explained next.
First, a reset signal RST and signals PGM1 and PGM2 are set at a high level. Due to this, the first memory nodes N1a and N2a of latch circuits Q1 and Q2 are drawn to the ground level. As a result, the latch circuits Q1 and Q2 are cleared.
Next, a word line voltage is made to be 2.4V and a read operation is performed. The bit line voltage is held at a precharge voltage due to the fact that a cell current does not flow when the threshold voltage Vth is higher than the word line voltage (2.4V), and a high level is sensed. Conversely, when the threshold voltage Vth is lower than the word line voltage (2.4V), a cell current flows, so that the bit line voltage falls and a low level is sensed.
Next, a read operation is carried out when the word line voltage is at 1.2V, then, finally, at 0V.
Specifically, since a current does not flow in any word lines when the cell data is "00", (1, 1) is output to buses IO.sub.i+1 and IO.sub.i. First, when the word line voltage is made 2.4V for a read operation, the control signal .phi.LAT1 is set at a high level. At this time, the bit line is held at a high level due to the fact a cell current does not flow. Therefore, the NMOS transistor NT8 is kept in a conductive state. Due to the fact that the latch circuit Q2 is cleared, the second memory node N2b of the latch circuit Q2 is held at a high level. Therefore, the NMOS transistor NT11 is kept conductive. Accordingly, the NMOS transistors NT8, NT11, and NT12 are kept conductive, the second memory node N1b of the latch circuit Q1 is drawn to the ground level, and the first memory node N1a of the latch circuit Q1 shifts to a high level. Next, when making the word line voltage 1.2V for a read operation, the control signal .phi.LAT3 is set to a high level. At this time, due to the fact that the cell current does not flow, the bit line is held at a high level. Therefore the NMOS transistor NT13 is kept conductive, the second memory node N2b of the latch circuit Q2 is drawn to the ground level, the second memory node N2b of the latch circuit Q2 is drawn to the ground level, and the first node N2a of the latch circuit Q2 shifts to a high level. Finally, when making the word line voltage 0V for a read operation, the control signal .phi.LAT1 is set to be a high level. At this time, due to the fact that the cell current does not flow, the bit line is kept at a high level. Therefore, the NMOS transistor NT8 is kept conductive, however, since the second memory node N2b of the latch circuit Q2 is at a low level, the NMOS transistor NT11 becomes non-conductive and the first memory node N1a of the latch circuit Q1 is held at a high level.
When the cell data is "01", the current flows only when the word line voltage is VWL00 and (1, 0) is output to the buses IOi+1 and IOi. First, when reading with the word line voltage 2.4V, the control signal .phi.LAT1 is set to a high level. At this time, due to the fact that the cell current flows, the bit line becomes a low level. Therefore, the NMOS transistor NT8 is kept nonconductive and the first memory node N1a of the latch circuit Q1 is held at a low level. Next, when reading with the word line voltage 1.2V, the control signal .phi.LAT3 is set to a high level. At this time, due to the fact that the cell current does not flow, the bit line is held at a high level. Therefore, the NMOS transistor NT13 is kept conductive, the second memory node N2b of the latch circuit Q2 is drawn to the ground level, and the first memory node N2a of the latch circuit Q2 shifts to a high level. Finally, when reading with the word line voltage 0V, the control signal .phi.LAT1 is set to a high level. At this time, due to the fact that the cell current does not flow, the bit line is held at a high level. Therefore, the NMOS transistor NT8 is kept conductive, however, since the second memory node N2b of the latch circuit Q2 is at a low level, the NMOS transistor NT11 becomes nonconductive and the first memory node N1a of the latch circuit Q1 is held at a low level.
In the case where the cell data is "10" or "11", (0, 1) and (0, 0) are read respectively to IO.sub.i+1 and IO.sub.i in the same way.
Next, a write operation will be explained.
In the circuit of FIG. 2, a write operation is performed first by data stored in the latch circuit Q1, then by data stored in the latch circuit Q2, finally by data stored in the latch circuit Q1 again.
Here, in the case where the write data is (Q2, Q1)=(1, 0), the latch circuit Q1 inverts "0" to "1" when sufficiently written. In the case where (Q2, Q1)=(0, 0), the latch circuit Q1 does not invert "0" to "1" even when sufficiently written in the first step because it is necessary to use the data also as write data in the third step.
Regarding the judgement whether the write operation is completed in each of the steps, it is judged that the write operation is completed in the step at the stage when all of the latch data (Q2 or Q1) on the noted side is "1".
The judgement of completion by a wired-OR is not carried out to cells of write data (Q2, Q1)=(0, 0) because the latch circuit Q1 does not invert in the first step.
In the above circuit, as shown in FIG. 4, a write operation is performed on the cells having the write data "10" and "00" in accordance with the data of the latch circuit Q1 (Step 1), then, a write operation is performed on the cells having the write data "01" and "00" in accordance with the data of the latch circuit Q2 (Step 2), and finally, a write operation is performed on the cells having the write data "00" (Step 3).
Namely, in the above circuit, the write operation of the write data "10" and "01" is performed only at Step 1 and at Step 2, so that the write times of "10" and "01" as they are correspond to those of Step 1 and Step 2. The write operation is performed in all steps from Step 1 to Step 3 on the cells having the write data "00", however, between Step 2 and Step 3, the write operation in Step 3 is performed after the ISPP voltage is reduced in preparation for excessive writing.
It is assumed from the above that the write time of a cell having the write data "00" is almost the same as the write time in Step 3. As a result, the write operation is performed serially. This is a cause for the write time of four-level data becoming long.
As will be understood from FIG. 4, the sum of the write time of data "10" and "01" is almost the same as the write time of data "00".
Also, the write operation is carried out by using a self-boost; however, a write inhibit voltage charged on the bit lines drops by the threshold voltage Vth to Vcc-Vth (B) (where Vth(B) is the threshold voltage Vth affected by back bias) due to the NMOS transistor to which signals PGM1 and PGM2 are supplied.
To enable self-boosting under this condition, it is necessary that the select gate on the drain side of the memory cell be set to be high, which becomes an obstacle for the realization of a high speed read operation.
Furthermore, the bit line is charged before the write operation in the latch; however, the bit line is a huge capacitor having the voltage 0V when looking from the latch. Thus, when the latch data is "1", there is a possibility that the latch data will invert at the moment of contact with the bit line.
To avoid the above, the gate voltage of the NMOS transistors NT5 and NT7 go down roughly 2V when charging the bit line in accordance with the write data. Therefore, the charging current becomes small and the bit line takes a long time to charge.
It also takes time for a verify read operation.
The above disadvantages become further serious in the case where the level of the multi-level data is still higher, for example, as shown in FIG. 5 in the case of eight-level data in which the distribution of the threshold voltage is divided into eight, from a distribution 0 to distribution 7.
In order to meet recent demands for higher integration, it can be considered to further increase the levels of multi-level data. Therefore, it is necessary to realize high speed write and verify operations even in the case of eight-level data etc.